A cache memory device known in the art that includes a main memory and a cache memory prefetches data at a prefetch address from the main memory to the cache memory. Japanese Laid-Open Patent Publication No. 9-259040 describes a cache memory device including an address calculation circuit. The address calculation circuit determines a prefetch address based on cache control information that is added to data.
However, when cache control information is added to data, the memory requires extra capacity for the added data. Thus, even though the speed of cache determinations may be increased, the efficiency for accessing the memory is reduced. This decreases the data processing speed. Further, data containing cache control information is generated under the assumption that it will be accessed by a processor. Thus, such data is not versatile.